In driving volatile memories such as DRAMs (Dynamic Random Access Memories), a refresh operation is performed after a write operation and before loss of stored data so that the stored data is retained. For example, whereas a DRAM discriminates 0's and 1's from each other depending on the amount of electric charges stored in capacitors, the charges stored in the capacitors decrease with time. Therefore, a rewrite operation is done by the refresh operation while the discrimination between 0's and 1's is enabled, thus making it possible to retain the storage.
Conventionally, it has been practiced that power is normally supplied to the memory section that cyclically performs the refresh operation in the standby mode in which none of the write operation, the erase operation and the read operation is performed.
In the prior art, however, there has been a problem that because the power is normally supplied to the memory section even in the standby mode, power consumption would increase, so that reduction of the power consumption of the equipment is inhibited.